1. Field of the Invention
The present invention relates generally to an interposer fabricating process and a wafer packaging structure, and more specifically to an interposer fabricating process and a wafer packaging structure formed by the interposer without through silicon vias and adhesive.
2. Description of the Prior Art
As the technology of semiconductor fabrication grows more advanced, relevant techniques have to be developed to fulfill the requirements of the semiconductor devices. The fabrication process of a semiconductor device typically includes three stages. In the first stage, an epitaxy technique may be used for the formation of a semiconductor substrate. Semiconductor devices such as metal-oxide semiconductor (MOS) and multilevel interconnection are fabricated on the substrate in the second stage.
The third stage is the packaging process. It is now a leading trend to fabricate a device or an electronic product with a thin, light, and small dimension; that is, with a higher integration for semiconductor devices. In terms of packages, many techniques such as chip scale package and multi-chip module (MCM) have been developed to obtain this high integration. The development of a fabrication technique with a line width of 0.18 μm has evoked a great interest, and led to intensive research to further decrease the package volume. It is one of the most important package techniques that can arrange more than one chip into a single package. In a multi-chip package, chips of the processor, memory (including dynamic random access memory (DRAM) and flash memory), and logic circuit can be packed together in a single package, which reduces both the fabrication cost and the packaging volume. The signal transmission path is shortened to enhance the efficiency. The multi-chip IC packaging technology can be applied to a multi-chip system with variable functions and operation frequencies.
There are many styles of packaging, such as flip chip bonding, wire bonding, flip chip combining wire bonding or utilizing interposers. In current processes, packaging by interposers is widely used, wherein TSV (through silicon via) structures are used in the interposers for interconnections between dies or between a die and the substrate to provide electrical connection of the components on each level. This technique can provide a relatively high routing density and very fine pitch with good electrical performance. Interposers utilizing TSV and adhesive for physically connecting these components need complex processes, however, which can cause defects. This may lead to unpredictable problems in a formed device, which decreases the reliability of its performance.